1. Field of Art
This disclosure generally relates to techniques for testing embedded integrated circuits. In particular, and without limitation, the present disclosure relates to systems and methods for testing embedded memory instances formatted as a memory hard macro.
2. Description of the Related Art
Embedded memories consume an ever-increasing amount of die area in a wide variety of system-on-chip (SoC) devices. Driven partially by advances in semiconductor process technologies, die area populated with embedded memory cover greater than eighty percent of the overall die area in many SoCs. And because embedded memory may cover a substantial amount of die area, embedded memory can be more vulnerable to defects resulting from wafer fabrication and other manufacturing and assembly steps. Reduced feature size resulting from advance semiconductor process technologies may also increase the probability of the occurrence of fabrication defects.
To improve test coverage for faults resulting from these defects, SoC designers may use a combination of design for test techniques. For example, some design for test techniques target the embedded memory instance. Other design for test techniques may target verification of one or more signal paths that include input pins coupled to receive external data, test logic surrounding the memory instance, and output pins coupled to transmit the received data. Additional design for test techniques may include adding standardized interface logic around each embedded memory instance to facilitate testing of multiple embedded memory instances individually, in parallel, or in a daisy-chain manner.
Adding test or shadow logic specialized for a particular design for test technique may improve fault coverage at the expense of performance density. Additional test logic consumes die area that could otherwise be used for the functional operation of the SoC. And for many high speed designs, surrounding a memory core with additional test logic increases the routing complexity to the memory instance and protracts timing closure.
It is therefore desirable to have systems or methods to provide improved design for test methodologies that optimize SoC performance density and reduce the efforts associated with timing closure.